1. Field of the Invention
The present invention generally relates to a semiconductor memory device including a fuse box, and more specifically, to a semiconductor memory device including a fuse box wherein the layout of a fuse box used to control a memory cell array is improved, a fuse box is divided into a plurality of blocks, and an index mark is applied to every fuse box or to every block so that a user may recognize each fuse box.
2. Description of the Prior Art
Due to development of semiconductor process technology, the size of a unit cell in a semiconductor memory device decreases, which results in reduction of the size of cell matrix.
A semiconductor memory device comprises a cell matrix and a fuse box corresponding to the cell matrix. The fuse box is used for repair or test.
Conventionally, the size of the cell matrix and the fuse box relatively do not matter when the layout of the cell matrix and the fuse box is determined.
As shown in FIG. 1, a row of a fuse box 12 is arranged in each cell matrix 10. Power meshes 14 are arranged at both ends of the fuse box 12. A cutting area 16 is defined inside of the fuse box 12. The fuse box area 12 is defined by a fuse barrier layer 18 wherein fuses are formed.
As the unit cell becomes smaller, the size of the cell matrix 10 becomes smaller. However, there is little change in the size of the fuse box 12 due to its material.
As a result, the size of the cell matrix 10 becomes relatively smaller than that of the fuse box 12, and the layout of the fuse box 12 should be changed to overcome the relative disproportion in size.